1. Field of the Invention
The invention relates to the field of complementary metal-oxide-semiconductor (CMOS) integrated circuit processing.
2. Prior Art
In the fabrication of complementary MOS transistors, guardbands are employed between the complementary devices to reduce parasitic current paths. Numerous processes are known for forming these guardbands, for example, see U.S. Pat. Nos. 4,013,484 and 4,282,648. As will be seen the present invention provides a unique process for forming the guardbands, and in particular a process is disclosed where the guardbands are self-aligned within a well.
CMOS integrated circuits are known to have a number of advantages over p-channel or n-channel circuits, such as high noise immunity, low power consumption and a very high resistance to soft failures associated with ionizing radiation. One major problem with CMOS circuits is their tendency to become "latched." Numerous transistor-like parasitic paths are formed in CMOS circuits and damaging currents flow through these paths when the circuit becomes latched. One proposed solution to the latching problem includes the use of a highly conductive substrate and the formation of active devices in an epitaxial layer grown on the substrate. In its presently preferred embodiment, the invented process is used with such an epitaxial layer.